sn54lv04a, sn74lv04a hex inverters scls388h ? september 1997 ? revised july 2003 1 post office box 655303 ? dallas, texas 75265 2-v to 5.5-v v cc operation max t pd of 6.5 ns at 5 v latch-up performance exceeds 250 ma per jesd 17 typical v olp (output ground bounce) <0.8 v at v cc = 3.3 v, t a = 25 c typical v ohv (output v oh undershoot) >2.3 v at v cc = 3.3 v, t a = 25 c support mixed-mode voltage operation on all ports i off supports partial-power-down mode operation esd protection exceeds jesd 22 ? 2000-v human-body model (a114-a) ? 200-v machine model (a115-a) ? 1000-v charged-device model (c101) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1a 1y 2a 2y 3a 3y gnd v cc 6a 6y 5a 5y 4a 4y sn54lv04a ...j or w p ackage sn74lv04a . . . d, db, dgv, ns, or pw package (top view) 3212019 910111213 4 5 6 7 8 18 17 16 15 14 6y nc 5a nc 5y 2a nc 2y nc 3a 1y 1a nc 4y 4a v 6a 3y gnd nc sn54lv04a . . . fk package (top view) cc nc ? no internal connection sn74lv04a . . . rgy package (top view) 114 78 2 3 4 5 6 13 12 11 10 9 6a 6y 5a 5y 4a 1y 2a 2y 3a 3y 1a 4y v gnd cc description/ordering information these hex inverters are designed for 2-v to 5.5-v v cc operation. the ?lv04a devices contain six independent inverters. these devices perform the boolean function y = a . these devices are fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. ordering information t a package ? orderable part number top-side marking qfn ? rgy reel of 1000 sn74lv04argyr lv04a soic d tube of 50 sn74lv04ad lv04a soic ? d reel of 2500 sn74lv04adr lv04a sop ? ns reel of 2000 sn74lv04ansr 74lv04a ?40 c to 85 c ssop ? db reel of 2000 sn74lv04adbr lv04a tube of 90 SN74LV04APW tssop ? pw reel of 2000 SN74LV04APWr lv04a reel of 250 SN74LV04APWt tvsop ? dgv reel of 2000 sn74lv04adgvr lv04a cdip ? j tube of 25 snj54lv04aj snj54lv04aj ?55 c to 125 c cfp ? w tube of 150 snj54lv04aw snj54lv04aw lccc ? fk tube of 55 snj54lv04afk snj54lv04afk ? package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. copyright ? 2003, texas instruments incorporated unless otherwise noted this document contains production data information current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
sn54lv04a, sn74lv04a hex inverters scls388h ? september 1997 ? revised july 2003 2 post office box 655303 ? dallas, texas 75265 function table (each inverter) input a output y h l l h logic diagram, each inverter (positive logic) y a absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, v cc ? 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 1) ? 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high-impedance or power-off state, v o (see note 1) ? 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o (see notes 1 and 2) ? 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0) ? 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o (v o = 0 to v cc ) 25 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v cc or gnd 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, ja (see note 3): d package 86 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see note 3): db package 96 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see note 3): dgv package 127 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see note 3): ns package 76 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see note 3): pw package 113 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see note 4): rgy package 47 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. this value is limited to 5.5 v maximum. 3. the package thermal impedance is calculated in accordance with jesd 51-7. 4. the package thermal impedance is calculated in accordance with jesd 51-5.
sn54lv04a, sn74lv04a hex inverters scls388h ? september 1997 ? revised july 2003 3 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 5) sn54lv04a sn74lv04a unit min max min max unit v cc supply voltage 2 5.5 2 5.5 v v cc = 2 v 1.5 1.5 v ih high level in p ut voltage v cc = 2.3 v to 2.7 v v cc 0.7 v cc 0.7 v v ih high - level input voltage v cc = 3 v to 3.6 v v cc 0.7 v cc 0.7 v v cc = 4.5 v to 5.5 v v cc 0.7 v cc 0.7 v cc = 2 v 0.5 0.5 v il low level in p ut voltage v cc = 2.3 v to 2.7 v v cc 0.3 v cc 0.3 v v il low - level input voltage v cc = 3 v to 3.6 v v cc 0.3 v cc 0.3 v v cc = 4.5 v to 5.5 v v cc 0.3 v cc 0.3 v i input voltage 0 5.5 0 5.5 v v o output voltage 0 v cc 0 v cc v v cc = 2 v ? 50 ? 50 a i oh high level out p ut current v cc = 2.3 v to 2.7 v ? 2 ? 2 i oh high - level output current v cc = 3 v to 3.6 v ? 6 ? 6 ma v cc = 4.5 v to 5.5 v ? 12 ? 12 v cc = 2 v 50 50 a i ol low level out p ut current v cc = 2.3 v to 2.7 v 2 2 i ol low - level output current v cc = 3 v to 3.6 v 6 6 ma v cc = 4.5 v to 5.5 v 12 12 v cc = 2.3 v to 2.7 v 200 200 ? t/ ? v input transition rise or fall rate v cc = 3 v to 3.6 v 100 100 ns/v v cc = 4.5 v to 5.5 v 20 20 t a operating free-air temperature ? 55 125 ? 40 85 c note 5: all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v sn54lv04a sn74lv04a unit parameter test conditions v cc min typ max min typ max unit i oh = ? 50 a 2 v to 5.5 v v cc ? 0.1 v cc ? 0.1 v oh i oh = ? 2 ma 2.3 v 2 2 v v oh i oh = ? 6 ma 3 v 2.48 2.48 v i oh = ? 12 ma 4.5 v 3.8 3.8 i ol = 50 a 2 v to 5.5 v 0.1 0.1 v ol i ol = 2 ma 2.3 v 0.4 0.4 v v ol i ol = 6 ma 3 v 0.44 0.44 v i ol = 12 ma 4.5 v 0.55 0.55 i i v i = 5.5 v or gnd 0 to 5.5 v 1 1 a i cc v i = v cc or gnd, i o = 0 5.5 v 20 20 a i off v i or v o = 0 to 5.5 v 0 5 5 a c i v i =v cc or gnd 3.3 v 2.3 2.3 p f c i v i = v cc or gnd 5 v 2.3 2.3 pf product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54lv04a, sn74lv04a hex inverters scls388h ? september 1997 ? revised july 2003 4 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended operating free-air temperature range, v cc = 2.5 v 0.2 v (unless otherwise noted) (see figure 1) parameter from to load t a = 25 c sn54lv04a sn74lv04a unit parameter (input) (output) capacitance min typ max min max min max unit t pd a y c l = 15 pf 7.1* 11.7* 1* 14* 1 14 ns t p d a y c l = 50 pf 10 15.5 1 18 1 18 ns * on products compliant to mil-prf-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, v cc = 3.3 v 0.3 v (unless otherwise noted) (see figure 1) parameter from to load t a = 25 c sn54lv04a sn74lv04a unit parameter (input) (output) capacitance min typ max min max min max unit t pd a y c l = 15 pf 5.1* 7.1* 1* 8.5* 1 8.5 ns t p d a y c l = 50 pf 7.3 10.6 1 12 1 12 ns * on products compliant to mil-prf-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, v cc = 5 v 0.5 v (unless otherwise noted) (see figure 1) parameter from to load t a = 25 c sn54lv04a sn74lv04a unit parameter (input) (output) capacitance min typ max min max min max unit t pd a y c l = 15 pf 3.6* 5.5* 1* 6.5* 1 6.5 ns t p d a y c l = 50 pf 5.1 7.5 1 8.5 1 8.5 ns * on products compliant to mil-prf-38535, this parameter is not production tested. noise characteristics, v cc = 3.3 v, c l = 50 pf, t a = 25 c (see note 6 ) parameter sn74lv04a unit parameter min typ max unit v ol(p) quiet output, maximum dynamic v ol 0.3 0.8 v v ol(v) quiet output, minimum dynamic v ol ? 0.1 ? 0.8 v v oh(v) quiet output, minimum dynamic v oh 3.1 v v ih(d) high-level dynamic input voltage 2.31 v v il(d) low-level dynamic input voltage 0.99 v note 6: characteristics are for surface-mount packages only. operating characteristics, t a = 25 c parameter test conditions v cc typ unit c pd power dissi p ation ca p acitance c l =50 p f f=10mhz 3.3 v 9.6 p f c p d power dissi ation ca acitance c l = 50 f , f = 10 mhz 5 v 11.4 f product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54lv04a, sn74lv04a hex inverters scls388h ? september 1997 ? revised july 2003 5 post office box 655303 ? dallas, texas 75265 parameter measurement information 50% v cc v cc v cc 0 v 0 v t h t su voltage waveforms setup and hold times data input t plh t phl t phl t plh v oh v oh v ol v ol v cc 0 v 50% v cc 50% v cc input out-of-phase output in-phase output timing input 50% v cc voltage waveforms propagation delay times inverting and noninverting outputs output control output waveform 1 s1 at v cc (see note b) output waveform 2 s1 at gnd (see note b) v ol v oh t pzl t pzh t plz t phz v cc 0 v 50% v cc v ol + 0.3 v 50% v cc 0 v v cc voltage waveforms enable and disable times low- and high-level enabling t plh /t phl t plz /t pzl t phz /t pzh open drain open v cc gnd v cc test s1 v cc 0 v 50% v cc t w voltage waveforms pulse duration input notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 1 mhz, z o = 50 ? , t r 3 ns, t f 3 ns. d. the outputs are measured one at a time with one input transition per measurement. e. t plz and t phz are the same as t dis . f. t pzl and t pzh are the same as t en . g. t phl and t plh are the same as t pd . h. all parameters and waveforms are not applicable to all devices. from output under test c l (see note a) load circuit for 3-state and open-drain outputs s1 v cc r l = 1 k ? gnd from output under test c l (see note a) test point load circuit for totem-pole outputs open 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc v oh ? 0.3 v figure 1. load circuit and voltage waveforms
mechanical data mpds006c february 1996 revised august 2000 1 post office box 655303 ? dallas, texas 75265 dgv (r-pdso-g**) plastic small-outline 24 pins shown 14 3,70 3,50 4,90 5,10 20 dim pins ** 4073251/e 08/00 1,20 max seating plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 112 24 13 4,30 4,50 0,16 nom gage plane a 7,90 7,70 38 24 16 4,90 5,10 3,70 3,50 a max a min 6,60 6,20 11,20 11,40 56 9,60 9,80 48 0,08 m 0,07 0,40 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. d. falls within jedec: 24/48 pins mo-153 14/16/20/56 pins mo-194
mechanical data msoi002b ? january 1995 ? revised september 2001 1 post office box 655303 ? dallas, texas 75265 d (r-pdso-g**) plastic small-outline package 8 pins shown 8 0.197 (5,00) a max a min (4,80) 0.189 0.337 (8,55) (8,75) 0.344 14 0.386 (9,80) (10,00) 0.394 16 dim pins ** 4040047/e 09/01 0.069 (1,75) max seating plane 0.004 (0,10) 0.010 (0,25) 0.010 (0,25) 0.016 (0,40) 0.044 (1,12) 0.244 (6,20) 0.228 (5,80) 0.020 (0,51) 0.014 (0,35) 1 4 8 5 0.150 (3,81) 0.157 (4,00) 0.008 (0,20) nom 0 ? 8 gage plane a 0.004 (0,10) 0.010 (0,25) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). d. falls within jedec ms-012
mechanical data msso002e ? january 1995 ? revised december 2001 1 post office box 655303 ? dallas, texas 75265 db (r-pdso-g**) plastic small-outline 4040065 /e 12/01 28 pins shown gage plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 ? 8 0,10 0,09 0,25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150
mechanical data mtss001c january 1995 revised february 1999 1 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
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